Transistor flip-flop indicator circuit



Aug- 7, 1962 J. c. SMELTZER 3,048,823

TRANSISTOR FLIP-FLOR INDICATOR CIRCUIT Filed Aug. l5, 1957 States iliteThis invention relates to transistor trigger circuits, and, moreparticularly, to means-for indicating the present state of a transistorbistable state circuit, such as a flip-Hop.

In electronic digital computers which express numbers in binary form,bistable state circuits such as hip-flops are frequently included tostore signals representing the digits. The development of the transistorhas led to the use of transistor stage-s in the mechanization of theiiip-op circuit. The resulting advantages have been circuit simplicity,reliability, small size and weight, and low power consumption.

The static type of dip-flop, of which the Eccles-Jordan trigger circuitis representative, is characterized by two stable states, namely, a truecondition in which one trigger stage conducts current and the othertrigger stage is cut oif, and the false7 condition in which theconduction of the stages is reversed. The storage of a digit l may beconsidered to be the existence of the true condition `and the storage ofa ydigit 01" may be considered to be the existence of the falsecondition. Digit recognition may be manifested by the voltage levels ona pair of output lines, one line being associated with each stage of theflip-flop.

Provision for visual indication of the binary content of the staticflip-flop `may be made by means of a circuit whereby a relay coil isconnected in the output line of one of the iiip-iop trigger stages, landthe relay contacts are arranged to control the power supply of anincandescent lamp indicator. This yarrangement -may require the4inclusion of components incidental to the function of visualindication; thus, for satisfactory operation at a high switching rate,it is necessary to include a shunt circuit to compensate for theinductance of the relay coil. Further, since the loop introduced by theshunt circuit is characterized by the building up of oscillatingcurrents, there is required a unilateral conducting device such `as acrystal diode to damp out these oscillations. lt is, of course,undesirable to make provisions such as these, since they add to computersize and complexity.

In another type of indicator circuit, an isolating stage, which may be atransistor amplier, is connected to the output circuit of one of theHip-flop trigger stages. An incandescent lamp and a source of powertherefor are serially connected as a load for the isolating transistor.The expenditure of power in this type of circuit is considerable and ifa neon lamp were utilized instead of the incandescent lamp, the size ofthe required voltage supply for the neon lamp would not be commensuratewith that required by the other components of a transistorized computersystem.

Neither of the above techniques is adaptable to 4the'indication of thecontent of the phase bistable type of flipflop.

The phase bistable fiip-op is a dynamic type in that the continuousswitching of the Hip-flop from a true state to a false state mayrepresent the digit 1, andthe continuous switching of the flip-hop fromthe false state to the true state may represent the digit 0. Thus theoutput of this ip-op is a square wave form, the phase of-which, whenreferenced to the period of a timing signal, is taken to indicatewhether it is storing a digit 1 or a digit O. It is apparent that theaforementioned indicator systems 3,048,823 Patented Aug. 7, 1962 wouldgive the same indication for either digit content of this type offlip-flop.

The recurring, i.e., A.C., nature of the phase bistable flip-flop outputrequires that the means provided to detect the storage condition besynchronized with the switching of the ilip-iiop in order that the digitpresently being stored be not recognized as its dual. As will'be shownherein, a means admirably suited `for this function is a referenceliip-ilop which may be of the same construction as the storage flip-Hop.The reference flip-Hop is arranged to continuously generate a signaloutput corresponding to one of the digits, for instance, the digit 1.Generation of this digit 1 by the reference Hip-flop is in synchronismwith the generation of the digit presently being stored by the storageip-op: for each digit output from the latter, be it a digit l or a digit0, the reference flip-nop generates a digit l in synchronism therewith.The outputs of the flip-flops are conveyed to a phase detector whichproduces an output during a timing period comprising a square wavevoltage only if its inputs are in phase for the timing period;otherwise, the phase detector output is a steady state voltage. Itfollows that a square wave Voltage output from the phase detectorindicates that a digit 1 is presently contained in the storage iiip-op,and a steady state voltage output from the phase detector indicates thata digit 0` is presently contained in the storage dip-flop. In thepreferred embodiment of the invention, the phase detector is shown inthe form of an and gate. The and gate output is ampliied by a transistoramplifier stage and the amplified signal is transformer coupled to aneon lamp indicator and series resistor. The turns ratio of secondary toprimary windings on the transformer is sufficiently high to develop thetiring voltage for the neon lamp and the windings are characterized bytime constants long enough so that the square `wave energ-ization ispassed substantially undistorted. Since, as is generai practice inelectronic computer work, the frequency of the timing signal is high, onthe order of kc./ sec., which exceeds the ila-Shing rate capability ofthe ordinary neon lamp, the square wave input to the transformer causesthe lamp to be continuously energized. Thus, when there is coincidenceof phase between the storage flip-Hop and the reference flipop,indicating that the storage ip-op is storing a digit l, the -larnp iscontinuously lit, and, when there is lack of such coincidence,indicating that the storage flip-flop is storing a digit O, the lamp iscontinuously extinguished.

It is thus a primary object of this invention to provide an improvedindicator circuit for use with transistor trigger circuits, especiallythose of the phase bistable flip-flop type.

It is a further object of this invention to provide an improvedtransistor flip-Hop i-ndicator circuit requiring no power supply otherthan that which supplies the transistor stages.

It is another object of this invention to provide a flipiiop indicatorcircuit isolated from the ip-iiop Vso that the oper-ation of theflip-flop is not adversely affected by the presence of the indicatorcircuit.

Other objects and many of the features of the invention will becomeapparent with reference to the following description of the figures, inwhich:

FIGURE l is the circuit of the preferred embodiment of the invention;

FIGURE 2 are waveshapes at the indicated points in FIGURE 1,corresponding to an example of the .operation of the circuit.

Referringnow to FIGURE 1, here is shown the preferred form of thecircuit of the invention.

Flip-flop `10 and 16 are identical, and, for the purposes ofillustration, will be considered to be of the phase bis-table type andto be functionally Iassociated with the logic of a computer. Inputs toreference ilip-ilop 1d are from the computer clock (timing) signals onlysince the digit content thereof is not modified. Inputs to storageHip-flop 16 are from logical networks such as gates, controlled by othercomputer signals, which may be flip-op outputs, timing signals, etc.

Considering storage flip-flop 16, complementary outputs are taken alines 18 and 28 and comprise symmetrical square wave forms having +3 v.and -3 v. alternations. ll` `lip-tlop 16 may be switched to interchangethe phase of the output waveshapes at the occurrence of clock signalpulses. These clock pulses may be generated from a timing signal channelon a rotating drum, for instance, or by other means well known in theart. The phase shown, in which the right-hand output of a lipilop, hereon line 18 for Hip-flop 16, during a timing signal period, is -trst atthe high potential of +3 v. and then at the low potential of -3 v. (theflip-dop is true, then false), will be understood to represent thestorage of a digit 1 by the flip-flop, and the opposite phase, in whichthe right-hand output, during a timing signal period, is rst at the lowpotential of -3 v. and then at the high potential of +3 v. (the`llip-tlop is false, then true), will be understood to represent thestorage of a digit 0. Thus, FIGURE 1 illustrates the storage of a digit1 in both both ip-ops 10 and 16.

Reference flip-Hop 10 is not subject to change of digit content, sincethe output thereof is employed to indicate the ystorage content of aplurality of Hip-flops in the computer, the output on line 12 beingconveyed to other gates for this purpose.

Lines 12 and 18 of nip-flops 1() and 16, respectively, are connected asinputs to and gate 22. And gate 22 preferably is comprised of a pair ofinput crystal diodes 44 and 46, joined to line 4S, which is connectedthrough resistor 42 .to the positive potential source of +12 v. ,Diodes-44 and 46 are orientated so that whenever the input signals, on lines12 and 18, are both at a high potential of +3 v., the output, on line48, is at +3 v. Any time one or both of the signals on lines 12 and 18is at a potential lower than +3 v., the output on line 48 is also atthis potential.

A stage of isolation and amplitication follows and gate 22. Theamplifier comprises N-P-N transistor 24 loaded by the primary winding oftransformer 32. The base electrode of transistor 24 is connected to line48, the emitter electrode is connected to ground, and the collectorelectrode is connected to one terminal of the primary winding oftransformer 32, the other terminal thereof being connected to the +12 v.supply. The secondary winding of transformer 32 is loaded by neon lamp50 and current-limiting resistor 40 connected serially. Preferably,transformer 32. comprises a miniature toroid having windings of No. 36wire and a primary to secondary winding ratio of 1:6. It is alsocharacterized by long inherent time constants for its windings, and thusis capable of passing square Waves of repetition rate equivalent to thebasic digit (clock) timing period without appreciable distortion.Indicator lamp t) may be type 'Ne2 and transistor 24 may be type 2N167.It may thus be appreciated that the indicator circuit corresponding toeach computer storage Hip-flop may be of quite small size and bepackaged as a unit having but four connections: one to reference ip-flop10, one to its storage lilip-ilop, one to the D.C. supply voltage, andone to ground.

The operation of the circuit of FIGURE l can best be appreciated throughobservation of the waveshape graphs of tFIGiURE 2, wherein lines I andIl present typical operating voltage outputs of reference flip-flop(line 12) and of storage flip-nop 16 (line 18). It should be appreciatedthat outputs could be taken instead from lines 14 and 20, lines 14 and`18, or lines 12 and 21B (FIG- URE 1) of the corresponding flip-flops,depending upon whether the digit 1 or digit 0 storage state of storageflipop 16 is desired to be indicated by lamp Si), or upon loadingcriteria for the dip-flops, or upon any other relevant consideration incomputer design. The arrangement shown is preferred for illustration,however, since it is customary to indicate the digit 1 state of astorage hipflop. Further, it may be pointed out lthat the preferred`dynamic Hip-flops are arranged to be capable of changing storagecontent between a digit 1 and a digit O at the rise (leading edges) ofrecurring computer clock pulses, in; dicated in FIGURE 2 by verticalmarks 52. The time separation between succeeding Vertical marks 52coni-A prises the basic computer digit (clock) period. It mayadditionally be noted that the preferred flip-Hops are arranged tochange state between true and false in the center of a digit period;this is accomplished by means of a recurring timing signal (not shown),of the same repeti tion rate as the computer clock signal, whichappropriately energizes the input gates of the flip-iops Line III ofFIGURE 2 shows the phase relationship of outputs on lines 12 and 18 ofilipflops 10 and 16, re spectively, for the example contemplated. It isseen that, for the time extent of the graphs, the outputs are in phasefor two digit periods, then, for one digit period each, out of phase, inphase and out of phase. It is, of course, desired that the indicatorcircuit cause lamp 50` (FIGURE 1) to be illuminated for time periodsproportional to the number of in-phase successive digit periods.

Line IV of lFIGURE 2 shows that the output on line 48 of and gate 22(FIGURE l) is at ground potential only when flip-flops 10 and 16 aresimultaneously true, for which condition lines 12 and 18 are at the +3v. level. This can occur only during the first half of a digit periodand, in the illustration, is shown to prevail during the tirst, secondand fourth digit periods of the selected sequence. The rise of lines 12and 18 to +3 v. results in decreased current through diodes 44 and 46.The voltage on line 48 rises, but cannot exceed ground potential sincetransistor 24, connected in a grounded emitter circuit with base bias of01V. draws current for any base voltage in excess thereof, thusetfectively clamping positive-going excursions of voltage on line 48 atground potential.

When flip-flops 10 and 16 are not both true, such as occurs during thesecond half of every digit period and also during the -trst half of thedigit periods during which the flip-flops are not both storing a digit1, the base of transistor 24 (line 48) is biased at the -3 v. level and`current from collector to emitter of transistor 24 is cut olf. For thiscondition, line 48 is terminated in a high impedance; the leading edgeof the voltage on line 48 y(line zIV) thus follows very closely that ofthe leading edge or edges of the ip-flop outputs (lines I and II).However, when the ilip-ops are both storing a digit 1, their outputssimultaneously drop to -3 v. at the center of the digit period. At thesetimes (the first, second and fourth digit periods) diodes 44 and 46conduct increased current while transistor 24 suddenly stops drawingcollector to emitter current. Thus at each fall of potential of line 48from 0 to -3 v. the primary of transformer 32 is shock excited, as shownin line V, and has induced therein voltage excursions 54, which, it maybe noted, extend from the center of a digit period to slightly beyondits end. The amplification of the shock excitations in transformer 32are effective to energize lamp 50, as indicated in line VI.

It may be further noted that, Whenever only one iiipflop goes true, suchas at the end of the second digit period and at the center of the lifthdigit period (lines I and Il), a pulse of voltage occurs on line 48.Pulses 56 (line IV) are representative. Pulses 56 are extremely sharpand eiect but slight shock excitation of transformer 32, as shown byoscillations 58 (line V). The ratio of windings of transformer 32 issuch that the induced secondary voltage caused by oscillations 58 isi11- sufiicient to energize lamp 58.

It should be understood that the present indicator circuit is notlimited, as illustrated, to the comparison of the states of only twoflip-hops; the states of a large number of hip-flops could besimultaneously compared merely by connecting the appropriate output ofeach flipop through a diode to line 48, In this case, indicator lamp 50would illuminate only if all the flip-flops are storing the same binarydigit; such an arrangement may nd use as, for instance, a binarycomparator circuit.

From the foregoing description, it should be apparent that the presentindicator circuit is adaptable to cooperate with llip-op circuits otherthan the phase bistable type used for illustration. It should further beapparent that the circuit is also not limited to the elements shown.Thus, the transistor amplifier might well be of the PNP type, in whichcase the form of and gate 22 could be modified by one skilled in the artto provide operation equivalent to the preferred form; the indicatingdevice, although illustrated as a neon lamp, might be of a typecharacterized by a different principle of operation, such as a meter,electronic eye, recorder or the like; the and gate might be an alternatetype of phase detection circuit such as used in oscilloscope ortelevision circuitry, having a relatively high input impedance so as notto affect the normal operation of the flip-flops. Such substitution ofelements may be made without sacrifice of reliability or certain otheradvantages and is contemplated by the invention as within the scope ofthe appended claims.

What I claim as new and desire to secure by Letters Patent of the UnitedStates is:

1. Circuit means for indicating the phase relationship between theoutputs of a pair of synchronized phase bistable flip-flops, comprising:a pair of crystal diode rectiiers having anode and cathode elements, thecathode elements being connected one to each flip-flop output and theanode elements being connected to a common line; a source of positivepotential; a resistor connected between said positive potential sourceand the common line; a current multiplication transistor having a baseelectrode connected to the common line, .an emitter electrode connectedto ground, and a collector electrode; a step-up transformer having aprimary winding and a secondary winding, the primary winding beingconnected between said positive potential source and the collectorelectrode of said transistor; and an ionizable lamp indicator andprotective resistor therefor connected serially across the secondarywinding of said transformer.

2. A circuit for indicating a signal output from a storage phasebistable flip-flop capable of having digit 1 or digit t) storage content`during predetermined periods, the indicated signal output thereofcorresponding to the storage of a digit 1, comprising: a reference phasebistable ilip-flop synchronized to generate a digit 1 output for eachand every signal output corresponding to the storage of either digit bythe storage ip-op; a detector circuit having inputs connected to theoutputs of the storage ilip-op and said reference flip-flop, saiddetector circuit being capable of generating a pulse signal during aperiod for which the ip-flops are simultaneously generating digit 1signals; and an indicator circuit responsive to the pulse signalgenerated by said detector circuit.

3. A circuit for indicating the storage content of a bistable statecircuit, comprising: a reference bistable state circuit synchronized tochange state each and every time the storage bistable state circuit isable to change storage content; a phase detector capable of generating apulse signal upon detection of an in-phase relationship between thestorage bistable state circuit and said reference bistable statecircuit; amplifier means for the pulse signal output from said phasedetector; an indicator; and a step-up transformer having its primarywinding connected in the output circuit of said amplifier and itssecondary winding loaded by said indicator; said indicator comprising anionizable lamp.

4. Circuit means for indicating the phase relationship between theoutputs of a pair of synchronized phase bistable flip-flops, comprising:a logical and circuit having inputs connected to the outputs of saidflip-flops; a positive potential source; a resistor connected betweensaid positive potential source and the output of said and circuit; acurrent multiplication transistor having a base electrode also connectedto the output of said and circuit output, an emitter electrode connectedto ground, and a collector electrode; a step-up transformer having aprimary winding and a secondary winding, the primary winding beingconnected between said positive potential source and the collectorelectrode of said transistor; and an indicator loading the secondarywinding of aid transformer, said indicator comprising an ionizable amp.

References Cited in the file of this patent UNITED STATES PATENTS2,615,127 Edwards Oct. 21, 1952 2,641,696 Woolard `Tune 9, 195312,700,148 McGuigan Jan 18, 1955 2,776,420 Woll Ian. 1, 1957 2,814,019Bender Nov. 19, 1957 2,864,006 Vandeven Dec. 9, 1958 2,878,298Giacolleto Mar. 17, 1959 2,900,620 Johnson Aug. 18, 1959

